The present invention relates to a method by which sets of values representing various parameters can be allocated to addresses, at which addresses data pertaining to the various value sets can be stored in memory.
One such method can be employed in a switching method known as Asynchronous Transfer Mode (ATM), among others, a method that is used in so-called broadband ISDN or B-ISDN, for instance.
The Consultative Committee for International Telephony and Telegraphy (CCITT) already called on the switching method known as Asynchronous Transfer Mode (ATM) in May 1990 as a standard for so-called data packet switching in B-ISDN. It defines ATM as follows: xe2x80x9cA switching method in which the information is bunched in cells; the method is asynchronous in the sense that the cells need not necessarily be exchanged periodically between the transmitter and the receiverxe2x80x9d. One possible embodiment for performing the ATM method is shown in FIG. 4.
The system shown there includes a switching station, which outputs data packets (ATM cells) received over first lines correspondingly to the respective destination site over second lines, and vice versa.
The first lines are glass fiber cables terminated by first termination units. The first termination units are the practical embodiment of so-called PHYs (physical ports).
The second lines, which are also embodied as glass fiber cables, are terminated by second termination units. Like the first termination units, the second termination units are the practical embodiment of so-called phys (physical ports).
The switching station includes a first ATM unit (shown on the left in FIG. 4), a second ATM unit (shown on the right in FIG. 4), and a coupling network disposed between them.
The first termination units are connected to the first ATM unit, and the second termination units are connected to the second ATM unit.
The ATM cells arriving at the switching station, or more precisely at the ATM units thereof, have a cell header in which, among other information, the destination site or the receiver of the particular ATM cell is defined in a 28-bit address field.
The 28-bit address has two components, namely a 16-bit VCI part and a 12-bit VPI part. VCI stands for Virtual Channel Identifier and designates the connection end point to which the useful data contained in the applicable ATM cell are to be switched. VPI stands for Virtual Path Identifier and designates a subscriber system that includes many connection end points, to which system the useful data contained in the applicable ATM cell are to be switched.
The first and second ATM units include a non-illustrated connection status information memory, in which for each connection, or more precisely for each VPC (Virtual Path Connection) and for each VCC (Virtual Channel Connection), which is made via the switching station, certain data (connection status information) are stored. The data to be stored include approximately 200 bytes per connection, and thus are relatively extensive.
The 28 bits in the header region of each ATM cell reserved for specifying the receiver of a given ATM cell make it possible to establish 228 different connections. If a memory region large enough to enable storing the aforementioned connection status information in it were to be reserved for each of the connections in this enormous number of possible connections, this would require the provision of a memory with a huge storage capacity.
A memory with such a large storage capacity is feasible only at the greatest possible technological effort and expense, since in practice only an extremely small fraction of the theoretically possible number of connections is or can be made at the same time and each is used for only an extraordinarily small fraction of the time.
It is therefore preferable to use a memory whose storage capacity is oriented xe2x80x9conlyxe2x80x9d to the maximum number of connections that can be made simultaneously. In that case, however, the memory can no longer be addressed directly through the 28-bit address in the header region of the ATM cells. Instead, it requires address conversion or a special address allocation. More precisely, it requires the use of a method by which sets of values representing various parameters can be assigned to addresses at which data pertaining to the various value sets can be stored; the various parameters in the example here are VPI, VCI, and possibly also PN (Physical Port Number) and which is the number of a termination unit or a line over which the applicable ATM cell was received. The address to be assigned to the various value sets will hereinafter be called the LCI (for Logical Channel Identifier).
In performing such allocations, it is known to make use of an (auxiliary) memory that is preoccupied with values in such a way that the address (LCI) to be allocated to a given value set (VPI, VCI, PN) is either the address of that memory region whose contents correspond to the value set, or the contents of the memory region that can be addressed using the value set as an address.
The first of these cases is practically feasible by using a so-called content addressable memory (CAM) as the (auxiliary) memory. In CAMs, a comparator is provided for each memory region, and by this comparator data (value sets) applied to the memory can each be compared with the contents stored in the applicable memory region. This comparison is performed simultaneously for all the memory regions by the comparators assigned to the various memory regions and is therefore done very quickly. As a result, the address of the row in which the data corresponding to the value set are stored is obtained; this row address is at the same time the address LCI to be assigned to the value set. It can be appreciated that this kind of practical embodiment of the address allocation is relatively complicated, because of the large number of comparators that must be provided and operated simultaneously.
The second case above can be embodied by a xe2x80x9cnormalxe2x80x9d (auxiliary) memory, which is preferably subdivided hierarchically into a plurality of memory units. Such a system is shown in FIG. 5. It includes a first memory unit, a second memory unit, and a third memory unit The first memory unit is addressed by the physical port number PN; the second memory unit is addressed on the basis of the virtual path identifier VPI, or more precisely by a base address PVPI+VPI obtained from the first memory unit, and the third memory unit is addressed on the basis of the virtual channel identifier VCI, or more precisely by a base address PVCI+VCI obtained from the second memory unit. The data stored at the various addresses of the individual memory units are either directly the addresses (LCI) to be allocated to the applicable value sets, or are pointers P, which point to the beginning of an assigned memory region of the respectively lower-ranking memory unit. For among other reasons because of the fact that the LCI values to be ascertained and allocated in real time are obtained by an intrinsically slow, multistage method, this kind of practical realization of address allocation again proves to be relatively complex.
This kind of multistage method for ascertaining an address with a reduced number of bits is known from U.S. Pat. No. 5,481,687.
It is also known from U.S. Pat. No. 5,557,609 to extract an ATM cell from the 28-bit address in the header region by shifting the VPI and VCI parts bit by bit. By subsequently shortening the VPI and VCI values, an address with a reduced number of bits is generated for addressing a memory that contains conversion data.
The above-described methods, however, require not only complex hardware, that is, high-speed and/or extensive hardware, but also, for instance when the system configuration is expanded and/or changed, because of the (auxiliary) memory expansion or expansions then required and/or the change in memory contents then required, can be adapted to the altered conditions only at relatively major effort and expense.
It is accordingly an object of the invention to provide a method by which sets of values representing various parameters can be allocated to addresses that overcomes the above-mentioned disadvantages of the prior art methods of this general type, in which the address allocation sought is always feasible in a simple way and at minimal effort and expense.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method by which sets of values representing various parameters can be allocated to addresses, and at the addresses, data pertaining to the sets of values can be stored in memory, which includes: forming allocated addresses from address components formed by concatenation of individual values of a value set, and at least one of a scope of the address components and an order of the address components in the concatenation can be varied individually in dependence on configuration parameters that have an influence on ranges of values of the various parameters.
It is accordingly provided that the allocated addresses are each formed by a concatenation of address components representing the individual values of a given set of values, and the scope of the various address components and/or the order of the various address components in their concatenation can be varied individually as a function of configuration parameters that have an influence on the ranges of values of the parameters.
The address to be allocated to a given set of values is accordingly no longer, as was the case previously obtained by using an association table realizable by an auxiliary memory or the like, but instead by the concatenation of address components representing the values of the applicable value set in a way adapted to given conditions.
Accordingly, a method which includes corresponding the address components to values of a given set, canceling elements of no significance for address forming, and replacing canceled elements with other elements has been provided.
The few circumstances (configuration parameters) on which the generation of the address to be allocated depends, and the few and slight effects thereof on address forming (change in the length and order of the concatenated address components) are advantageous in two respects. First, the hardware to be furnished for performing the method can be of low complexity and structured simply. Second, for adaptation of the method to changed circumstances, all that is required is to modify a few parameters representing the applicable circumstances.
Accordingly, a method has been discovered through which the sought address allocation can always be realized simply and at minimal expense.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method by which sets of values representing various parameters can be allocated to addresses, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.